Modern electronic devices often include a variety of electrical and electronic circuits. For example, a computing device such as a smartphone or tablet may include one or more processor or Digital Signal Processor (DSP) circuits with associated memory; one or more Radio Frequency (RF) modem circuits for radio connectivity; a display driver circuit; and various signal processing circuits, such as a satellite positioning receiver, audio or video processing circuits; and the like. These disparate circuits often have different power supply requirements, such as different required DC voltage levels.
Many modern electronic devices are portable, and are powered by batteries—either replaceable batteries such as alkaline cells, or rechargeable batteries such as NiCd, NiMH, LiOn, or the like. In either case, the useful life of portable electronic devices is limited by available battery power, which decreases in proportion to the length of use of the device, and the level of power consumption during that use. With each generation of most electronic devices, form factors shrink, due to increasing integration of electronics and miniaturization of component parts, such as disk drives, while simultaneously new features and functionality are added, increasing the component count and/or computational load. Both trends exacerbate the problem of limited available power. Shrinking devices force the size of the battery to shrink as well, which generally reduces the available energy storage capacity, while at the same time the battery must power more components, or drive processors at higher speeds. These factors have made power management a critical area of optimization for electronic device designers.
One known adaptive power management approach is to identify circuits (or sub-circuits) that are not used for extended periods, and put them into a low-activity state, also referred to as a “sleep mode,” even if other circuits in the device are fully active. As one example, the illuminated display screen of many devices will shut off after a (selectable) duration of no user interactivity. A straightforward way to shut down a particular electronic circuit is to interrupt the power supplied to that circuit. Since the remainder of the device is still active, a plurality of individually-enabled power supply circuits is required.
FIG. 1 depicts a portion of one known power management system 10. A main voltage reference circuit 12 generates and maintains a precise reference voltage. The main reference voltage is distributed to a plurality of regulator voltage reference circuits 14A, 14B, 14C. Each of the regulator voltage reference circuits 14A-C generates a reference voltage for a downstream voltage regulator (not shown), by dividing the main reference voltage by a factor of K, where K=[1, infinite]. For example, the regulator voltage reference circuit 14A may output 12 VDC and its associated voltage regulator drives analog RF circuits; regulator voltage reference circuit 14B may output 5 VDC and its associated voltage regulator drives discrete digital logic; and regulator voltage reference circuit 14C may output 3.3 VDC and its associated voltage regulator drives a microprocessor and memory. Each regulator voltage reference circuit 14A-C is independently enabled by a control circuit (not shown) via separate enable signals. The associated voltage regulators may be enabled/disabled by the same enable signals as their regulator voltage reference circuits 14A-C.
FIG. 2 depicts a common configuration for a representative regulator voltage reference circuit 14N. Each regulator voltage reference circuit 14N includes, for example, a voltage setting circuit, which may be a resistive voltage divider network comprising resistors 16, 18, operative to reduce the reference voltage by a predetermined factor. Selective enabling of the regulator reference voltage output is provided by interposing a switch 20, such as a MOSFET transistor, in series with the voltage setting circuit 16, 18. The switch 20 is controlled by the enable_N signal, possibly through a buffer 22 to provide drive strength and conform the signal assertion level to the particular type of transistor used. When the regulator voltage reference circuit 14N is disabled, the switch 20 interrupts current flow to the voltage setting resistors 16, 18, reducing the output voltage to zero. The system may later enable the regulator voltage reference circuit 14N by turning the switch 20 ON, or rendering it fully conductive, via the enable_N signal. In this manner, each regulator voltage reference circuit 14A, 14B, 14C (FIG. 1) may be separately disabled and enabled as desired or required.
FIG. 3 depict a deleterious effect of the power management system of FIGS. 1 and 2. As a representative regulator voltage reference circuit 14N is enabled, and its switch 20 rendered conductive, the sudden load induces a transient voltage drop and current spike on the main reference voltage signal. This, in turn, induces a transient voltage drop on the regulator reference voltage signals output by all other currently-enabled regulator voltage reference circuits. Such noise on the power supply lines can have deleterious effects on the associated voltage regulators, and subsequently on the circuits supplied by the voltage regulators. For example, power supply glitches can randomly cause some—but not all—digital storage devices to change state, which may have disastrous consequences as processors, state machines, status registers, and the like are clocked into unknown and unintended states.
Prior art approaches to mitigating the deleterious effects of switching noise in enabling regulator voltage reference circuits include the use of RC-filters. However, resistors and capacitors can consume significant area on an integrated circuit. Additionally, in many cases the switching noise is transferred to the ground plane of the RC capacitor, which may disturb sensitive circuits sharing the same ground.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.